Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

The search for energy efficient circuital implementations of neural networks has led to the exploration of phase-change memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted non-idealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-the-art PCM programming techniques

Dual-mode wake-up nodes for IoT monitoring applications: Measurements and algorithms

Internet of Things (IoTs)-based monitoring applications usually involve large-scale deployments of battery-enabled sensor nodes providing measurements at regular intervals. In order to guarantee the service continuity over time, the energy-efficiency of the networked system should be maximized. In this paper, we address such issue via a combination of novel hardware/software solutions including new classes of Wake-up radio IoT Nodes (WuNs) and novel data- and hardware-driven network management algorithms. Three main contributions are provided. First, we present the design and prototype implementation of WuN nodes able to support two different energy-saving modes; such modes can be configured via software, and hence dynamically tuned. Second, we show by experimental measurements that the optimal policy strictly depends on the application requirements. Third, we move from the node design to the network design, and we devise proper orchestration algorithms which select both the optimal set of WuN to wake-up and the proper energy-saving mode for each WuN, so that the application lifetime is maximized, while the redundancy of correlated measurements is minimized. The proposed solutions are extensively evaluated via OMNeT++ simulations under different IoT scenarios and requirements of the monitoring applications

From Heterogeneous Sensor Networks to Integrated Software Services: Design and Implementation of a Semantic Architecture for the Internet of Things at ARCES@UNIBO

The Internet of Things (IoTs) is growing fast both in terms of number of devices connected and of complexity of deployments and applications. Several research studies an- alyzing the economical impact of the IoT worldwide identify the interoperability as one of the main boosting factor for its growth, thanks to the possibility to unlock novel commercial opportunities derived from the integration of heterogeneous systems which are currently not interconnected. However, at present, interoperability constitutes a relevant practical issue on any IoT deployments that is composed of sensor platforms mapped on different wireless technologies, network protocols or data formats. The paper addresses such issue, and investigates how to achieve effective data interoperability and data reuse on complex IoT deployments, where multiple users/applications need to consume sensor data produced by heterogeneous sensor networks. We propose a generic three-tier IoT architecture, which decouples the sensor data producers from the sensor data consumers, thanks to the intermediation of a semantic broker which is in charge of translating the sensor data into a shared ontology, and of providing publish-subscribe facilities to the producers/consumers. Then, we describe the real-world implementation of such architecture devised at the Advanced Research Center on Electronic System (ARCES) of the University of Bologna. The actual system collects the data produced by three different sensor networks, integrates them through a SPARQL Event Processing Architecture (SEPA), and supports two front- end applications for the data access, i.e. a web dashboard and an Amazon Alexa voice service

What's in a Sign? Trademark Law and Economic Theory

Abstract: The aim of this paper is to summarise the extant theory as it relates to the economics of trademark, and to give some suggestions for further research with reference to distinct streams of literature. The proposed line of study inevitably looks at the complex relationship between signs and economics. Trademark is a sign introduced to remedy a market failure. It facilitates purchase decisions by indicating the provenance of the goods, so that consumers can identify specific quality attributes deriving from their own, or others', past experience. Trademark holders, on their part, have an incentive to invest in quality because they will be able to reap the benefits in terms of reputation. In other words, trademark law becomes an economic device which, opportunely designed, can produce incentives for maximising market efficiency. This role must, of course, be recognised, as a vast body of literature has done, with its many positive economic consequences. Nevertheless, trademark appears to have additional economic effects that should be properly recognized: it can determine the promotion of market power and the emergence of rent-seeking behaviours. It gives birth to an idiosyncratic economics of signs where very strong protection tends to be assured, even though the welfare effects are as yet poorly understood. In this domain much remains to be done and the challenge to researchers is open

Electronic Circuit for communicating through capacitive coupling

A device and method to compensate for distortions of amplitude that afflicts systems for communicating through capacitive coupling

Soft-Core eFPGA for Smart Power Applications

Nowadays Smart Power technologies are demanding smarter devices to give the opportunity of end-user customizations to reach best-in-class efficiency in applications such as sensing and power conversions. Reconfigurable devices \u2013 in the form of embedded FPGA (eFPGA) \u2013 can represent an effective solution to address such demand. Differently from CMOS world, where reconfigurable technologies have been widely proposed in the last two decades to couple flexibility and NRE costs reduction, eFPGAs targeting Smart Power applications is a new challenge that we can face today thanks to recent improvement of the digital capabilities of such technologies. In this paper we explore the implementation of a soft-core eFPGA tailored for Smart Power applications targeting STMicroelectronics BCD9s 0.11 \u3bcm technology. Area-optimized and speed-optimized implementations prove the existence of a significant design space, both in terms of area (~15%) and speed (~50%) variation. A set of benchmarking applications representative of different smart power fields (sigma-delta modulation, power management and motion control) have been mapped on a 16 CLBs eFPGA; the performance are discussed showing the potential added-value provided by reconfigurability

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

A receiver for capacitive coupled communication is embedded in a digital input/output pad to add the capacity for non-contact data communication, while maintaining size, ESD protection, and buffering functions unchanged, even in contact mode. The added feature allows non-contact probing of die pads and provides a reliable alternative solution to mechanical probing for electrical wafer sort testing of Systems-on-Chip (SoC) and Systems-in-Package (SiPs) because of elimination of pad damage and reduction of the force required to create stable electrical contacts between probe needles and pads. The proposed receiver detects the displacement current flowing through the capacitive channel created between the connecting probe needle and top metal pad surface when a transition in the input digital stimulus signal occurs. The receiver is designed to work up to 100 Mbit/s data rate with a power of 340 \u3bcW in a 40 nm CMOS process. The circuit trade-offs between frequency, amplitude of the step input and distance are discussed. Experimental results show that for a 5 V input voltage amplitude, the receiver allows correct data transmission at a distance up to 5 \u3bcm, which increases to 10 \u3bcm if the top aluminum layer is divided in two, using a customized I/O pad design. The feasibility of this non-contact testing approach was verified through electrical tests on two IP blocks, an LFSR, and a PLL with a scan chain, using a standard prober and a cantilever probe card designed with 19 needles of different lengths to enable both physical contact connections for power supply and non-contact capacitive coupling data communication for signals